1. Field of the Invention
The present invention relates to the improvement of the semiconductor device having the electrostatic discharge (hereinafter referred to as "ESD") resistance of an ESD protection element that protect an internal circuit from the breakdown due to an ESD.
2. Description of the Background Art
An integrated circuit is usually provided with a protection circuit in order to protect an internal circuit from the breakdown due to ESDs, such as discharge of the charge from the exterior, and discharge of the charge charged to the integrated circuit. An ESD protection element that comprises an MOS transistor or a field transistor utilizing a local oxidation of silicon (hereinafter referred to as "LOCOS") oxide film is used as a protection circuit. Generally, one electrode of a transistor serving as an ESD protection element is connected an I/O terminal, and the other electrode is connected to a fixed potential setting terminal, e.g., a ground terminal.
FIG. 25 is a circuit diagram showing a connection example of an NMOS transistor for protection. As shown in FIG. 25, the drain of an NMOS transistor for protection Q1 is connected to an I/O terminal P1, and the source and gate are grounded. An internal circuit (not shown) for performing the actual operation is also connected to the I/O terminal P1.
When the normal voltage is applied to the I/O terminal P1, the NMOS transistor for protection Q1 is in OFF state, causing no influence on the internal circuit. On the other hand, when an ESD occurs and the surge voltage SV is applied to the I/O terminal P1, the PN junction between an N type drain region and a P type well region (substrate) results in breakdown to discharge the surge voltage from the I/O terminal P1 to a ground level (grounding terminal), thereby protecting the internal circuit.
A field transistor has the structure in which an LOCOS oxide film is provided in place of the gate section (i.e., the gate oxide film and gate electrode) of an MOS transistor. Therefore, such a field transistor does not maintain the original transistor structure, but it is called field transistor in the technical fields that deal with ESD. Hereinafter, the regions of a field transistor which correspond to the drain and source regions of an MOS transistor are also referred to as drain and source regions, respectively.
An N type field transistor for protection (whose drain and source regions are of the N type) having the above-mentioned structure may be connected in the same manner as in the NMOS transistor for protection Q1 shown in FIG. 25. However, no potential setting is required for a LOCOS oxide film.
Like the MOS transistor for protection, in the field transistor for protection, no current follows between the drain and source in the normal state, and when an ESD occurs, the PN junction between the N type drain region and the P type well region results in breakdown so that a surge voltage is discharged from an I/O terminal P1 to a ground level (grounding terminal), to protect an internal circuit.
That is, the breakdown of the PN junction of an ESD protection element in the occurrence of an ESD allows the surge voltage to be discharged through the ESD protection element, thereby protecting the internal circuit. In prior art, an ESD protection element has been formed together with an internal circuit on a single semiconductor substrate under the same conditions.
However, as the refinement of elements is advanced, the ESD resistance of an ESD protection element is lowered, and therefore, even if an ESD protection element is formed inside an integrated circuit, failing to protect the breakdown due to an ESD.